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[VHDL-FPGA-Verilog] can.tar

Description: can控制器IP核，verilog语言描述实现。含测试例-can controller IP core, verilog language described realize. Containing the test cases
Platform: | Size: 54272 | Author: yu | Hits:

[USB develop] USBipcore

Description: usb1.1 ip核，使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog
Platform: | Size: 155648 | Author: liu | Hits:

[VHDL-FPGA-Verilog] usb11

Description: 基于verilog HDL的一个USB 1.1的IP 核，内有详细文档说明。-Verilog HDL based on a USB 1.1 of the IP core, which has detailed documentation.
Platform: | Size: 414720 | Author: 戴求淼 | Hits:

[Other Embeded program] CAST_jpeg_d-xact

Description: JPEG_D IP Core Verilog crypted source
Platform: | Size: 879616 | Author: Serg | Hits:

[Other Embeded program] cyc2_cmon_080805

Description: Verilog 8051 IP Core for Cyclone -Verilog 8051 IP Core for Cyclone II
Platform: | Size: 63488 | Author: Alx | Hits:

[VHDL-FPGA-Verilog] USB2.0IP

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码,包括文档-Complete Verilog language developed by USB2.0 IP core source code, including documentation
Platform: | Size: 206848 | Author: 陈润 | Hits:

[VHDL-FPGA-Verilog] CAN_IP

Description: 这是CAN总线控制器的IP核，源码是由Verilog HDL编写的。其硬件结构与SJA1000类似，满足CAN2.0B协议。-This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
Platform: | Size: 61440 | Author: 普林斯 | Hits:

[Embeded-SCM Develop] spi_op_core

Description: SPI协议的Verilog编程，包括时钟的产生模块，控制模块等-Verilog programming SPI protocol, including the selection of the clock module, control module, etc.
Platform: | Size: 82944 | Author: zhangyi | Hits:

[VHDL-FPGA-Verilog] DDS

Description: Quartus中实现的DDS 使用的是altera提供的IP core-DDS achieved Quartus using IP core provided by altera
Platform: | Size: 83968 | Author: ray | Hits:

[VHDL-FPGA-Verilog] 43680540SPI_Core

Description: Verilog for SPI Core source code
Platform: | Size: 14336 | Author: J.M Yang | Hits:

[VHDL-FPGA-Verilog] 107215786i2c_master_verilog

Description: Verilog for I2C core source code
Platform: | Size: 247808 | Author: J.M Yang | Hits:

[VHDL-FPGA-Verilog] DP8051_FREE

Description: Free 8051 core upload
Platform: | Size: 475136 | Author: zahir Parkar | Hits:

[VHDL-FPGA-Verilog] oc8051_verilog

Description: 兼容8051的内核oc8051，verilog版本的-8051-compatible core oc8051, verilog version of
Platform: | Size: 1251328 | Author: tong | Hits:

[VHDL-FPGA-Verilog] DW8051_ALL

Description: 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!
Platform: | Size: 1588224 | Author: myfingerhurt | Hits:

[VHDL-FPGA-Verilog] Revised_Verilog_code

Description: 简弘伦：Verilog HDL IC设计核心技术实例详解 源代码,更新版本-Honglun Jian, Revised Edition. Source coude of " Core Techniques of IC design"
Platform: | Size: 507904 | Author: 阿光 | Hits:

[VHDL-FPGA-Verilog] mc8051_design

Description: 8051内核的设计，用Verilog硬件描述语言实现，在modelsim环境下进行仿真。-8051-core design, using Verilog hardware description language, in the modelsim simulation environment.
Platform: | Size: 396288 | Author: huangguilin | Hits:

[Crack Hack] AES

Description: AES算法的verilog代码，即AES算法IP核-ip core for AES
Platform: | Size: 13312 | Author: JJ | Hits:

[VHDL-FPGA-Verilog] i2c

Description: 基于FPGA的I2C内核的verilog程序-Verilog program of I2C core base on FPGA.
Platform: | Size: 2379776 | Author: 李波 | Hits:

[VHDL-FPGA-Verilog] LatticeMico8_v3_0_Verilog

Description: The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with 16 or 32 General Purpose registers, the LatticeMico8 is a flexible Verilog and VHDL reference design suitable for a wide variety of markets, including communications, consumer, computer, medical, industrial, and automotive. The core consumes minimal device resources, less than 200 Look Up Tables (LUTs) in the smallest configuration, while maintaining a broad feature set.-The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with 16 or 32 General Purpose registers, the LatticeMico8 is a flexible Verilog and VHDL reference design suitable for a wide variety of markets, including communications, consumer, computer, medical, industrial, and automotive. The core consumes minimal device resources, less than 200 Look Up Tables (LUTs) in the smallest configuration, while maintaining a broad feature set.
Platform: | Size: 1155072 | Author: 郭豪偉 | Hits:

[VHDL-FPGA-Verilog] fft_verilog

Description: FFT IP core 源码 状态控制机-FFT IP core
Platform: | Size: 7168 | Author: chris | Hits:
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